This invention relates to the use of latch clocks during the design phase of an integrated circuit to achieve optimal integrated circuit performance for the master/slave latch design. In particular, this invention relates to adjusting system clocks allowing the machine frequency to increase, improving overall system performance and also to fix early mode timing problems that may have escaped integrated circuit timing.
In integrated circuit design, designers use latch based designs to eliminate race hazards. A circuit free of race hazards is easier to test and more reliable. In high performance computer systems, time stressing methods are used to time stress the system logic to determine the failure margins, or to detect and repair marginal or unstable errors. The stressing functions are useful in engineering, field engineering diagnostics and trouble-shooting. A technique called Level Sensitive Scan Design or LSSD is a type of scan design which uses separate system and scan clocks to distinguish between normal and test mode. Latches are often used in pairs with each latch having a normal data input, a data output and a clock. In order to perform test operations, the two latches form a master/slave pair with one scan input, one scan output and non-overlapping scan clocks which alternate. The scan in and scan out [scan] design is a technique which aims to increase the controllability and observability of the digital logic circuit by incorporating special scan registers into the circuit so that they form a scan path. For a more complete description of level sensitive logic systems and particularly system path stressing, reference is made to U.S. Pat. No. 4,564,943 issued Jan. 14, 1986 to Collins et al. and the references cited therein. The use of LSSD in digital computers has provided a minimization of race conditions, hazards and AC timing dependencies.
In the IBM(copyright) S/390(copyright) systems, for example, latch clocks are positioned so that during hardware testing, the location of the clocks chosen in the design stage can often be improved to account for differences between design assumptions and the actual xe2x80x9cas manufacturedxe2x80x9d hardware. The differences between the xe2x80x9cas designedxe2x80x9d integrated circuit and the xe2x80x9cas manufacturedxe2x80x9d integrated circuit create deviations in system performance. In the past, design methods allowed for the entire clock pulse to be moved to stress the late mode (also known as long paths) and early mode (also known as short paths) critical timing paths. However, the methods did not account for all of the critical timing paths (timings) associated with a master/slave clock system. In other words, extensive timing of the early mode and late mode timings was conducted, but because cycle times were still relatively slow, the pulse widths and the mid-cycle separation critical timing paths were set to work xe2x80x9cas designed.xe2x80x9d The pulse width and mid-cycle separation timing paths were not considered as problems because system frequencies were relatively slow in comparison to today. There was ample pulse width to account for deviations from the xe2x80x9cas designedxe2x80x9d system. The pulse width was designed oversized to allow for any deviation in the slower systems. However, as the system cycle times approach Ghz frequencies, all timing paths are becoming increasingly critical. Accordingly, there remains a need for a system and method for adjusting all critical timing paths in a system using master/slave latches by independently moving critical timing paths associated with the master/slave latch design.
An exemplary embodiment of the invention is a method and apparatus for configuring system cycle time in a data processing system with at least one master latch clock generating a master latch clock signal and at least one slave latch clock generating a slave latch clock signal. Timing errors are detected during system hardware testing. Adjustments to the system timing are calculated based on error for at least one of a master latch clock signal and a slave latch clock signal. The on-cycle edge of at least one of the master latch clock signal and slave latch clock signal is adjusted based on the calculations while maintaining a corresponding mid-cycle edge of at least one of the master latch clock signal and the slave latch clock signal.